(1) Field of the Invention
This invention relates to integrated circuit semiconductor devices, and more particularly to a method for fabricating dynamic random access memory devices having tungsten (W) landing plug contacts and titanium/titanium nitride (Ti/TiN) bit lines. This reduces the aspect ratio for multilevel contacts and provides a more reliable process for increased circuit density.
(2) Description of the Prior Art
As integrated circuit density increases, it becomes increasing difficult to manufacture ultra large scale integrated (ULSI) circuits. One of the problems associated with making these dense circuits is the increase in the number of material layers that result in the need to pattern high-aspect-ratio features in the underlying layers. One area of concern is the multilevel contact openings that must be etched to wire up the discrete devices on an integrated circuit. One area where this is of particular concern is the DRAM circuit. For example, the number of memory cells on the DRAM chip has dramatically increased in recent years, and is expected to reach 1 Gigabit by the year 2000. This increase in circuit density has resulted from the downsizing of the individual semiconductor devices (FETs), which is due in part to advances in high-resolution photolithography and directional (anisotropic) plasma etching. The downsizing has resulted in multilevel contact openings with very high aspect ratios. It is necessary to provide planar surfaces to form photolithographic images with good fidelity, but requires etching contact openings in relatively thick layers having large aspect ratios, for example greater than 7. This makes it difficult to etch the contact openings and to reliably fill the openings with metal contacts.
One method of circumventing this problem is to form landing plug contacts on the substrate to which the multilevel contact openings with reduced aspect ratios can be etched. For example, methods for forming self-aligned metal plugs to substrates have been reported in the literature. One method is described by Sung in U.S. Pat. No. 5,631,179 in which a Ti/TiN barrier layer and tungsten plugs are formed in the contact openings. An insulating layer is deposited and contact openings are formed. An AlCuSi layer is then deposited and patterned to connect the tungsten plugs. Another method for making contact plugs for integrated circuits is described by Fiordalice et al. in U.S. Pat. No. 5,534,462 in which a TiN barrier layer or glue layer is eliminated to reduce processing complexity. Instead, an aluminum nitride (AlN) is used as the glue layer to improve the tungsten adhesion to the insulating layer and the AlN does not have to be removed when the tungsten is patterned. Lur in U.S. Pat. No. 5,364,817 describes a method for making improved tungsten plugs that avoids voids in the plug (dog-bone structure), and protects the contact areas from junction failure and prevents failure due to stress in the contacts. Fazan et al., U.S. Pat. No. 5,130,885, teaches a method of making DRAM cells using a rough capacitor surface to increase capacitance. The capacitor is essentially flat and the DRAM structure is relatively thin, therefore Fazan does not address the need for etching high-aspect-ratio contacts.
Therefore there is still a need in the industry to provide a process that further reduce the aspect ratio of the multilevel contact openings in addition to the reduction achieved by using the prior-art method of including the landing plug contacts. It is also desirable to integrate the bit line and bit-line plug contacts in the memory cell area with the landing plug contacts in the peripheral area of the chip to provide a more cost-effective manufacturing process and to reduce the chip size.